Burst cycle data compression schemes for pre-fuse wafer-level test in large scale high-speed embedded DRAM

This paper describes two novel data compression schemes suitable for high density and high speed embedded DRAMs. The parallel compression serial readout scheme reduces bit-scan test times to one eighth. The parallel compression multiplexed readout scheme realizes high frequency at-speed tests even with low cost testers. Both can be used for pre-fuse wafer tests requiring redundancy calculations. The new schemes have been implemented in a test chip with a 65nm technology and verified.