1.8-V 800-Mb/s/pin DDR2 and 2.5-V 400-Mb/s/pin DDR1 compatibly designed 1Gb SDRAM with dual clock input latch scheme and hybrid multi-oxide output buffer

Author

Fujisawa, Hiroki ; Nakamura, M. ; Takai, Y. ; Koshikawa, Y. ; Matano, T. ; Narui, S. ; Usuki, N. ; Dono, C. ; Miyatake, S. ; Morino, M. ; Arai, K. ; Kubouchi, S. ; Fujii, I. ; Yoko, H. ; Adachi, T.

Author_Institution

Technol. & Dev. Office, Elpida Memory, Inc., Kanagawa, Japan

fYear

2004

Firstpage

38

Lastpage

39

Abstract

Two circuit techniques of DDR1/DDR2 compatible chip architecture designed for both high-speed and high-density DRAMs are presented. The dual clock input latch scheme, which reduces the excessive timing margin for random input commands by using a pair of latch circuits controlled by dual-phase 1-shot clock signals, achieves a 0.9-ns reduction in cycle time from 3.05 ns to 2.15 ns. By using these techniques in combination with a hybrid multi-oxide output buffer, we developed a 175.3 mm² 1Gb SDRAM which operates as a 800-Mb/s/pin DDR2 or 400Mb/s/pin DDR1.

Keywords

DRAM chips; flip-flops; 1 Gbit; 1.8 V; 1.8-v 800-Mb/s/pin DDR2; 1Gb SDRAM; 2.5 V; 2.5-v 400-Mb/s/pin DDR1; 3.05 to 2.15 ns; 400 Mbit; 800 Mbit; dual clock input latch scheme; hybrid multi-oxide output buffer; Circuits; Clocks; Frequency; Latches; Marine technology; Prefetching; SDRAM; Space vector pulse width modulation; Timing; Ultra large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346494

Filename

1346494