DocumentCode
1637004
Title
A Σ-Δ fractional-N synthesizer with a fully-integrated loop filter for a GSM/GPRS direct-conversion transceiver
Author
Hwang, In-Chul ; Lee, Han-Il ; Lee, Kun-Seok ; Cho, Je-Kwang ; Nah, Kyung-Suc ; Park, Byeong-Ha
Author_Institution
Syst. LSI Div., Samsung Electron. Co. Ltd., Yongin, South Korea
fYear
2004
Firstpage
42
Lastpage
45
Abstract
This paper presents a fractional-N synthesizer with a 3-bit 4th-order interpolative Σ-Δ modulator for a GSM/GPRS direct conversion transceiver. With an integrated VCO and an integrated loop filter, the synthesizer achieves the phase noise performances less than -78dBc/Hz at close-in offset and less than -116dBc/Hz at 400kHz offset. The chip was fabricated and evaluated in a 0.35 μm SiGe BiCMOS process.
Keywords
packet radio networks; radiotelephony; sigma-delta modulation; voltage-controlled oscillators; Σ-Δ fractional-N synthesizer; 0.35 micron; 400 kHz; GSM/GPRS direct-conversion transceiver; fully-integrated loop filter; integrated VCO; integrated loop filter; synthesizer; BiCMOS integrated circuits; Filters; GSM; Germanium silicon alloys; Ground penetrating radar; Phase noise; Silicon germanium; Synthesizers; Transceivers; Voltage-controlled oscillators;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8287-0
Type
conf
DOI
10.1109/VLSIC.2004.1346497
Filename
1346497
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