Design Test: a solution to the problems of ASIC verification

Assuming that adequate logic simulation and automatic test equipment are available, the authors note that there remain three major roadblocks associated with ASIC (application-specific integrated circuit) verification: efficiently generating logic simulations that thoroughly exercise the design; automatically and accurately verifying that the simulation results match the designer´s expectations; and automatically and accurately producing test vectors for ATE (automatic test equipment) which match the logic simulations. The authors describe Design Test, a technique that overcomes each of these roadblocks through a unique automated method of linking design and test using a software system approach. Design Test´s use of embedded tester knowledge early in the design process is a key factor in its capabilities. Not only does Design Test greatly increase the efficiency of ASIC verification, but it provides the means of increasing the thoroughness and accuracy of the verification activities as well