DocumentCode
1637453
Title
A 12 bit Continuous-Time ΣΔ modulator with 400MHz clock and low jitter sensitivity in 0.13 μm CMOS
Author
Patón, Susana ; Di Giandomenic, A. ; Hernández, Luis ; Wiesbauer, Andreas ; Pötscher, Thomas ; Clara, Martin
Author_Institution
Univ. Carlos III, Madrid, Spain
fYear
2004
Firstpage
82
Lastpage
83
Abstract
A wide bandwidth Continuous-Time ΣΔ lowpass ADC with a 4-bit internal quantizer is presented. The converter is implemented in a pure digital 0.13 μm CMOS. It achieves 76dB Dynamic Range over 12MHz signal bandwidth tolerating up to 20ps RMS clock jitter. Operated at 400MHz the power consumption is 70mW from a 1.5V supply. The ADC has been designed to be tolerant to excess-loop delay and clock jitter. The 4th-order loop-filter is based on OpAmp-RC structure.
Keywords
CMOS integrated circuits; analogue-digital conversion; jitter; sigma-delta modulation; 0.13 μm CMOS; 0.13 micron; 12 MHz; 12 bit Continuous-Time ΣΔ modulator; 20 ps; 400 MHz; 400MHz clock; 70 mW; excess-loop delay; low jitter sensitivity; lowpass ADC; Bandwidth; Circuits; Clocks; Delay; Delta modulation; Dynamic range; Feedforward systems; Jitter; Linearity; Topology;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8287-0
Type
conf
DOI
10.1109/VLSIC.2004.1346511
Filename
1346511
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