Title :
A 1V, 240 nW, 7 ppm/°C, high PSRR CMOS voltage reference circuit with curvature-compensation
Author :
Yuan, Pengpeng ; Li, DongMei ; Wang, Xin ; Liu, Liyuan ; Zhang, Chun ; Wang, ZhiHua
Author_Institution :
Instn. of Microelectron., Tsinghua Univ., Beijing, China
Abstract :
A low power voltage reference is implemented in a standard 0.18 μm CMOS process. The temperature coefficient (TC) of 7 ppm/°C is achieved in virtue of the output stage which consists of two transistors operating in subthreshold region and saturation region respectively. This kind of output stage is used to adjust the output voltage and compensate the curvature. The line sensitivity is 200 ppm/V in a supply voltage range of 1-3 V, and the power supply rejection ratio (PSSR) is -85 dB and -42 dB at 100 Hz and 10 kHz, respectively. The maximum supply current is 240 nA. The chip area is 0.016 mm2.
Keywords :
CMOS integrated circuits; reference circuits; transistors; CMOS process; PSRR CMOS voltage reference circuit; chip area; current 240 nA; curvature-compensation; frequency 100 Hz to 10 kHz; low power voltage reference; noise figure -85 dB to -42 dB; power supply rejection ratio; saturation region; size 0.18 mum; transistors; voltage 1 V to 3 V; CMOS integrated circuits; Photonic band gap; Temperature dependence; Temperature measurement; Temperature sensors; Transistors; Voltage measurement;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667671
