A 22mW 10-bit 150-MS/s pipelined ADC in 1.2V 65nm CMOS

This paper presents the low-power implementation of a 10-bit 150-MS/s pipelined analog-to-digital converter (ADC) in a standard 65 nm digital CMOS. The ADC removes the track-and-hold amplifier (THA) to reduce the power consumption. A 1.5 bit/stage architecture is used in the first stage to lower front-end design complexity. Three 2.5-bit stages are followed to reduce the stage number in the pipeline chain. Operational amplifiers (op-amps) sharing technique is used between consecutive stages for further power saving. A high swing continuous-time common mode feedback (CMFB) circuit is adopted in the op-amp design. Simulation results shows the proposed ADC achieves 9.8 ENOB with a 23 MHz input. The power consumption is 22 mW from a 1.2 V supply voltage. The active area is 640 μm × 470 μm.