A high-speed, transmission delay stability comparator

Author

Huang, Xingfa ; Li, Liang ; Zhang, Zhengping ; Chen, Liang

Author_Institution

Nat. Labs. of Analog Integrated Circuits, Chongqing, China

fYear

2010

Firstpage

457

Lastpage

459

Abstract

Based on the application of high-speed, high-resolution A/D converter, this paper describes the design and implementation of a novel high-speed comparator. The comparator uses the high-speed, transmission delay stability technology, the auto-zero technology, and the cascade technology in order for the comparator to have the high-speed, high-resolution, transmission delay stability features. Its performances are verified by a 14-bit 125MSPS pipelined A/D converter which is developed in 0.35um CMOS-based process technology. The SFDR of the A/D converter is up to 87 dB at an input clock of 125MHz with an input signal of 10MHz.

Keywords

CMOS integrated circuits; analogue-digital conversion; cascade networks; circuit stability; clocks; comparators (circuits); CMOS-based process technology; auto-zero technology; cascade technology; clock; frequency 10 MHz; frequency 125 MHz; high-resolution A/D converter; high-speed A/D converter; high-speed comparator; pipelined A/D converter; size 0.35 mum; transmission delay stability; word length 14 bit; Clocks; Converters; Delay; Frequency measurement; Latches; Preamplifiers; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667674

Filename

5667674