A novel cell-STP (storage node through plate node) cell-technology for multigigabit-scale DRAM and logic-embedded DRAM generations

A novel cell technology has been developed to overcome process issues related with successful downscaling of a DRAM memory cell and to produce a reliable and manufacturable cell. Storage node in the proposed cell is formed in a self-aligned manner through the plate node after the formation of plate node and capacitor dielectric. Considering the scalability of the novel cell and experimental results showing the charge storage capacitance of 25fF/cell, leakage current less than 1fA/cell, and excellent time-to-dielectric breakdown characteristics, it is expected that this novel cell technology can be a promising candidate for the 1Gb DRAM and beyond as well as logic-embedded DRAM.