Algorithms for synchronous logic synthesis

A new approach is presented to logic synthesis of digital synchronous sequential circuits. The authors describe algorithms for minimizing (i) the area of synchronous combinational and/or sequential circuits under cycle time constraints, and (ii) the cycle time under area constraints. Previous approaches attacked this problem by separating the combinational logic from the registers and by applying circuit transformations to the combinational component only. The authors show instead how to optimize concurrently the circuit equations and the register position. This method is novel and can achieve results that are at least as good as those obtained by previous methods. A computer implementation of the algorithms in the Minerva program is described