Author :
Yoshida, M. ; Asaka, K. ; Hoshino, Y. ; Sugawara, Y. ; Aoki, H. ; Saito, M. ; Imai, A. ; Enomoto, H. ; Kawakami, H. ; Furukawa, R. ; Fukuda, N. ; Tsuneno, K. ; Maeda, F. ; Kogayu, H. ; Ishikawa, I. ; Ogaya, K. ; Takakura, T.
Author_Institution :
Device Dev. Center, Hitachi Ltd., Tokyo, Japan
Abstract :
We have developed an embedded stacked DRAM technology that is integrated with 0.2 /spl mu/m CMOS logic and 6 level metalization. DRAM-based fabrication process enables a memory cell size of 0.405 /spl mu/m/sup 2/ with a 0.23 /spl mu/m design rule. This technology will enable a system-on-a-chip (SOC) with more than 100 Mbits of DRAM capacity on a practical chip size.
Keywords :
CMOS logic circuits; DRAM chips; embedded systems; integrated circuit metallisation; 0.2 micron; CMOS logic; embedded stacked DRAM technology; fabrication; memory cell; multilevel metallization; system-on-a-chip; CMOS logic circuits; CMOS technology; Logic devices; Random access memory; Silicides; Silicon compounds; System-on-a-chip; Thermal resistance; Tungsten; Ultra large scale integration;
