A high-performance 0.18-/spl mu/m merged DRAM/Logic technology featuring 0.45-/spl mu/m/sup 2/ stacked capacitor cell

Author

Hamada, M. ; Inoue, K. ; Kubota, R. ; Takeuchi, M. ; Sakao, M. ; Abiko, H. ; Kawamoto, H. ; Yamaguchi, H. ; Kitamura, H. ; Onishi, S. ; Koyanagi, K. ; Mikagi, K. ; Urabe, K. ; Taguwa, T. ; Yamamoto, T. ; Nagai, N. ; Shirakawa, I. ; Kishi, S.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1999

Firstpage

45

Lastpage

48

Abstract

This paper presents a 0.18-/spl mu/m merged DRAM/Logic technology having a 0.45-/spl mu/m/sup 2/ stacked capacitor cell. A low-temperature Metal/Insulator/Silicon (MIS) capacitor process provides high storage capacitance in the small cell, as well as a fully compatible process with high-performance CMOS logic technologies. A robust Co-salicide technology eliminates additional process steps for a silicide block. A developed 4 Mbit test vehicle achieves a retention time of 16 ms at 110/spl deg/C even with a CoSi/sub 2/ layer remaining on all diffusion regions in the memory cells.

Keywords

CMOS logic circuits; DRAM chips; MIS capacitors; 0.18 micron; 110 C; 4 Mbit; CMOS logic technology; Co salicide technology; CoSi/sub 2/; low-temperature MIS capacitor; memory cell; merged DRAM/logic technology; stacked capacitor cell; CMOS logic circuits; CMOS process; CMOS technology; Capacitance; Capacitors; Insulation; Metal-insulator structures; Random access memory; Robustness; Silicon on insulator technology;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823843

Filename

823843