A high-performance sample-and-hold circuit for 14-bit 125MS/s pipelined ADC

Author

Zhang, Rui ; Deng, Hong-Hui ; Yin, Yong-sheng ; Liang, Shang-Quan ; Gao, Ming-Lun

Author_Institution

Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China

fYear

2010

Firstpage

424

Lastpage

426

Abstract

This paper presents a design of a high-performance sample-and-hold (S/H) circuit. Switches´ constraints on signal settling in charge-transferring S/H circuit are discussed. Then the optimum combination of switches for this S/H circuit is proposed. Hspice simulated results based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows a 103dB SFDR, 86dB SNDR at Nyquist input @ Fs=125MS/s and preserves 91dB SFDR and 82dB SNDR with the input frequency up to 160MHz. The designed circuit has been used in the front end of 14-bit 125MS/s pipelined ADC adapted for single-ended applications.

Keywords

CMOS integrated circuits; SPICE; analogue-digital conversion; circuit simulation; integrated circuit design; sample and hold circuits; Hspice simulation; Nyquist input; SFDR; SNDR; charge-transferring S/H circuit; chartered CMOS process; designed circuit; front end; pipelined ADC; sample-and-hold circuit; signal settling; supply voltage; word length 14 bit; Capacitance; Clocks; Integrated circuit modeling; MOS devices; Semiconductor device modeling; Simulation; Switches;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667688

Filename

5667688