Sub 50-nm FinFET: PMOS

Author

Xuejue Huang ; Wen-Chin Lee ; Charles Kuo ; Hisamoto, D. ; Leland Chang ; Kedzierski, J. ; Anderson, E. ; Takeuchi, H. ; Yang-Kyu Choi ; Asano, K. ; Subramanian, V. ; Tsu-Jae King ; Bokor, J. ; Chenming Hu

Author_Institution

Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA

fYear

1999

Firstpage

67

Lastpage

70

Abstract

High performance PMOSFETs with gate length as short as 18-nm are reported. A self-aligned double-gate MOSFET structure (FinFET) is used to suppress the short channel effect. A 45 nm gate-length PMOS FinEET has an I/sub dsat/ of 410 /spl mu/A//spl mu/m (or 820 /spl mu/A//spl mu/m depending on the definition of the width of a double-gate device) at Vd=Vg=1.2 V and Tox=2.5 nm. The quasi-planar nature of this variant of the double-gate MOSFETs makes device fabrication relatively easy using the conventional planar MOSFET process technologies. Simulation shows possible scaling to 10-nm gate length.

Keywords

MOSFET; nanotechnology; semiconductor device measurement; semiconductor device models; 1.2 V; 18 nm; 2.5 nm; 45 nm; 45 nm gate-length; PMOS FinEET; device fabrication; double-gate device width; high performance PMOSFETs; planar MOSFET process technologies; quasi-planar nature; scaling; self-aligned double-gate MOSFET structure; short channel effect suppression; simulation; CMOS technology; Etching; Fabrication; FinFETs; Germanium silicon alloys; Laboratories; MOSFET circuits; Oxidation; Silicon germanium; Surface topography;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823848

Filename

823848