Title :
A multi-bit multiplying digital-to-analog converter with bi-directional overflow detection
Author :
Zhang, Rui ; Yin, Yong-sheng ; Liang, Shang-Quan ; Gao, Ming-Lun
Author_Institution :
Inst. of VLSI Design, Hefei Univ. of Technol., Hefei, China
Abstract :
A design of a 3.5 + 1-bit multiplying digital-to-analog converter (MDAC) which can be used in the first stage of a 14-bit 100MS/s pipelined analog-to-digital converter (ADC) is presented in this paper. Two decision levels are added in the MDAC so that bi-directional overflow of the input signal can be detected. Bootstrap structure with a buffer is proposed to prevent the large bootstrap capacitance from loading the front stage circuit of the MDAC. A two-stage high gain and wide unity gain bandwidth op-amp is designed. Simulation by Hspice based on Chartered 0.18μ 1P5M CMOS process under 1.8V supply voltage shows -84.23dB THD of the input sampling switches, 114dB open-loop gain, 2.5GHz unity gain bandwidth of the op-amp, and 11-bit resolution settling of the output signal of the MDAC.
Keywords :
CMOS integrated circuits; SPICE; analogue-digital conversion; bootstrap circuits; circuit simulation; digital-analogue conversion; multiplying circuits; operational amplifiers; ADC; Hspice; MDAC; bandwidth 2.5 GHz; bandwidth op-amp; bidirectional overflow detection; bootstrap capacitance; bootstrap structure; chartered CMOS process; circuit simulation; front stage circuit; input sampling switches; multibit multiplying digital-to-analog converter; open-loop gain; output signal; pipelined analog-to-digital converter; resolution settling; size 0.18 mum; unity gain bandwidth; voltage 1.8 V; Bandwidth; Bidirectional control; Capacitance; Integrated circuit modeling; Semiconductor device modeling; Signal resolution;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667689
