A novel CMOS analog neural oscillator cell

Author

Linares-Barranco, B. ; Sanchez-Sinencio, Edgar ; Newcomb, R.W. ; Rodriguez-Vazquez, Angel ; Huertas, J.L.

Author_Institution

Dept. of Electr. Eng., Texas A&M Univ., College Station, TX, USA

fYear

1989

Firstpage

794

Abstract

A very flexible programmable CMOS analog neural oscillator cell architecture is presented. The proposed neuron circuit architecture is a hysteretic neural-type pulse oscillator. Its implementation consists of a transconductance comparator, a capacitor, and two nonlinear resistors. It has over nine decades of oscillation frequency range, i.e., from 10 ^-2 Hz to 20 MHz. This range has been experimentally verified. The oscillator cell in the test chip was implemented in a standard 3-μm (p-well), double-metal CMOS technology and has a dimension of about 44000 μm² (without the capacitor). Preliminary measurements and simulated results agree very well

Keywords

CMOS integrated circuits; analogue circuits; comparators (circuits); neural nets; oscillators; 10^-2 Hz to 20 MHz; 3 micron; capacitor; double-metal CMOS technology; experimentally verified frequency range; flexible programmable CMOS analog neural oscillator cell architecture; hysteretic neural-type pulse oscillator; nonlinear resistors; oscillation frequency range; oscillator cell; p-well; preliminary measurements; simulated results; test chip; transconductance comparator; CMOS technology; Capacitors; Frequency; Hysteresis; Neurons; Oscillators; Pulse circuits; Resistors; Testing; Transconductance;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100470

Filename

100470