Analysis of transient error propagation in sub-powered CMOS circuits

The quest for lower power consumption has led to aggressive supply voltage scaling till near-threshold and sub-threshold regimes. Reliability represents one of the major concerns in these very low voltage conditions. This paper aims to study the occurrence and propagation of transient errors in noise-affected near and sub-threshold CMOS devices. We have performed SPICE simulation campaigns for 65 nm and 45 nm CMOS circuits operating at very low supply voltages. We have analyzed the impact of the amplitude and duration of pulses corresponding to the transient errors. Although the noise margins of the circuits are diminishing as the supply voltage is lowered, we noticed that transient error propagation is significantly hindered with the decrease in Vdd.