A self-calibrated binary weighted DAC in 90nm CMOS technology

Author

Arbet, D. ; Nagy, G. ; Stopjakova, V. ; Gyepes, G.

Author_Institution

Dept. of IC Design & Test, Slovak Univ. of Technol., Bratislava, Slovakia

fYear

2014

fDate

12-14 May 2014

Firstpage

383

Lastpage

386

Abstract

In this paper, an on-chip self-calibrated 8-bit R-2R digital-to-analog converter (DAC) based on digitally compensated input offset of the operational amplifier (OPAMP) is presented. To improve the overall DAC performance, a digital offset cancellation method was used to compensate deviations in the input offset voltage of the OPAMP caused by process variations. The whole DAC as well as offset compensation circuitry were designed in a standard 90nm CMOS process. The achieved results show that after the self-calibration process, the improvement of 48% in the value of DAC offset error can be obtained.

Keywords

CMOS digital integrated circuits; digital-analogue conversion; operational amplifiers; CMOS technology; OPAMP; digital offset cancellation method; digitally compensated input offset; input offset voltage; offset compensation circuitry; on-chip self-calibrated 8-bit R-2R digital-to-analog converter; operational amplifier; self-calibrated binary weighted DAC; size 90 nm; CMOS integrated circuits; CMOS technology; Calibration; Hardware; Standards; System-on-chip;

fLanguage

English

Publisher

ieee

Conference_Titel

Microelectronics Proceedings - MIEL 2014, 2014 29th International Conference on

Conference_Location

Belgrade

Print_ISBN

978-1-4799-5295-3

Type

conf

DOI

10.1109/MIEL.2014.6842170

Filename

6842170