The 2-phase on-demand delayed clock generator circuit

The phased clock signals are useful to synchronize the individual modules within a multiphase digital system and satisfy the complexity of their clock timing requirement. The capability of the on-demand adjustment of the phased clocking pattern can be embedded to the circuit that generates the associated clocks by shifting in time their active clock edges. A delay insertion technique is presented that can implement this adjustment capability. The designed two-phase circuit, targeting an FPGA device, generates the phased clock signals and has control inputs that define the timing and the positioning of delays. These clocks can directly drive the idle system modules to reduce their power consumption during the specified delay periods.