• DocumentCode
    1638464
  • Title

    A Futurebus+ central arbiter based on pairwise mutual exclusion

  • Author

    Dike, C. ; Ostler, Farrell

  • Author_Institution
    Signetics Co., Albuquerque, NM, USA
  • fYear
    1992
  • Firstpage
    195
  • Lastpage
    198
  • Abstract
    A scheme for building low-latency, first-come, first-served arbiters is presented. The basis of the scheme is pairwise mutual exclusion, which provides a fire wall for considerations of metastability. Cycles can occur, requiring a resolution mechanism, of which two are presented. A 14-channel, 7-ns arbiter for Futurebus+ has been fabricated in BiCMOS technology
  • Keywords
    BiCMOS integrated circuits; integrated logic circuits; system buses; 14-channel; 7 ns; BiCMOS technology; Futurebus+ central arbiter; first-come; first-served; low-latency; pairwise mutual exclusion; BiCMOS integrated circuits; Costs; Logic; MOS devices; Metastasis; Monitoring; Propagation delay; State-space methods; Switches; System recovery;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
  • Conference_Location
    Minneapolis, MN
  • Print_ISBN
    0-7803-0727-5
  • Type

    conf

  • DOI
    10.1109/BIPOL.1992.274052
  • Filename
    274052
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1638464