CMOS design for improved IC testability

Author

Favalli, M. ; Olivo, P. ; Damiani, M. ; Riccó, B.

Author_Institution

DEIS, Bologna Univ., Italy

fYear

1989

Firstpage

934

Abstract

Novel design-for-testability schemes are suggested to improve the detectability of transistor stuck-on faults, bridgings, and gate oxide shorts in CMOS digital circuits, with limited extra hardware and minimum degradation of circuit performance. One of the techniques makes analog faults detectable by observing the circuit outputs just as for stuck-ats. Also described is a technique in which the gates are modified with the insertion of n-channel FETs whose drains are the input of a ratioed NOR testing logic realized with n-channel drivers and a single resistive p-channel pull-up device

Keywords

CMOS integrated circuits; VLSI; fault location; integrated circuit testing; integrated logic circuits; logic testing; CMOS design; CMOS digital circuits; IC testability; NOR testing logic; VLSI; bridgings; design-for-testability; gate oxide shorts; n-channel FETs; n-channel drivers; resistive p-channel pull-up device; transistor stuck-on faults; CMOS digital integrated circuits; CMOS integrated circuits; Circuit faults; Circuit testing; Digital circuits; Electrical fault detection; Fault detection; Hardware; Integrated circuit testing; Logic testing;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82386

Filename

82386