3.3 volt sense-amplifier schemes suitable for 4 Mb BiCMOS SRAMs

Author

Suzuki, Azuma ; Kato, Hatsuhiro ; Kobayashi, Tomohiro ; Hamano, Takahiro ; Sato, Katsuhiko ; Matsui, Masataka ; Urakawa, Yukihiro ; Ochii, Kiyofumi

Author_Institution

Toshiba Corp., Kawasaki, Japan

fYear

1992

Firstpage

182

Lastpage

185

Abstract

The authors propose and discuss sense amplifiers suitable for low voltage operation. Compared with a conventional current sensing scheme, the hierarchical voltage sensing scheme reduces sensing delay by 39% and improves functional minimum voltage to 1.8 V, which is sufficiently low for a 3.3-V static RAM (SRAM). High-speed sensing techniques for 4-Mb VLSI SRAMs and beyond, and performance of a 9-ns, 4-Mb transistor-transistor-logic input/output SRAM implementing one of these sense amplifiers, are also presented

Keywords

BiCMOS integrated circuits; SRAM chips; 1.8 V; 3.3 V; 4 Mbit; 9 ns; BiCMOS SRAMs; LV operation; TTL I/O; hierarchical voltage sensing scheme; high-speed sensing; low voltage operation; sense-amplifier schemes; static RAM; transistor-transistor-logic input/output; BiCMOS integrated circuits; Bipolar transistors; Delay; Energy consumption; Low voltage; MOSFETs; Mirrors; Operational amplifiers; Random access memory; Very large scale integration;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0727-5

Type

conf

DOI

10.1109/BIPOL.1992.274055

Filename

274055