Title :
Noise reduction techniques for an ECL-CMOS RAM with a 2 ns write cycle time
Author :
Ohhata, Kenichi ; Sakurai, Yoshiaki ; Nambu, Hiroaki ; Kanetani, Kazuo ; Idei, Youji ; Hiramoto, Toshirou ; Tamba, Nobuo ; Yamaguchi, Kunihiko ; Odaka, Masanori ; Watanabe, Kunihiko ; Ikeda, Takahide ; Homma, Noriyuki
Author_Institution :
Hitachi Device Eng. Co. Ltd., Chiba, Japan
Abstract :
An ultra-high-speed ECL-CMOS static RAM (SRAM) with a cycle time of 2 ns has been developed. To achieve fast cycle time, three noise reduction techniques are proposed: which are a noise reduction clamp circuit for reducing the Y-select signal noise; a critical damping emitter follower for the overshoot noise; and a twisted-bit line structure with a normally on equalizer for the bit line crosstalk. The authors describe the noise generation mechanisms and the operation of circuits using each of the techniques. Experimental results are also described
Keywords :
BiCMOS integrated circuits; SRAM chips; crosstalk; emitter-coupled logic; interference suppression; 2 ns; ECL-CMOS RAM; SRAM; Y-select signal noise; bit line crosstalk; clamp circuit; critical damping emitter follower; equalizer; noise generation mechanisms; noise reduction techniques; overshoot noise; static RAM; twisted-bit line structure; ultra-high-speed; write cycle time; Bipolar transistors; Capacitance; Circuit noise; Clamps; Crosstalk; Damping; Equalizers; Noise generators; Noise reduction; Random access memory;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992
Conference_Location :
Minneapolis, MN
Print_ISBN :
0-7803-0727-5
DOI :
10.1109/BIPOL.1992.274057
