High quality ultra-thin (1.5 nm) TiO/sub 2/-Si/sub 3/N/sub 4/ gate dielectric for deep sub-micron CMOS technology

Author

Xin Guo ; Xiewen Wang ; Zhijiong Luo ; Ma, T.P. ; Tamagawa, T.

Author_Institution

Dept. of Electr. Eng., Yale Univ., New Haven, CT, USA

fYear

1999

Firstpage

137

Lastpage

140

Abstract

This paper presents the physical and electrical properties of ultra-thin (/spl sim/1.5 nm EOT) TiO/sub 2//Si/sub 3/N/sub 4/ gate dielectrics fabricated by the jet-vapor deposition (JVD) process for both n- and p-channel field-effect transistors. It will be shown that the use of TiO/sub 2//Si/sub 3/N/sub 4/ to replace SiO/sub 2/ as gate dielectric can reduce the gate leakage current by several orders of magnitude while maintaining excellent interface quality, high reliability, low trap density, and competitive n-and p-channel MOSFET performance.

Keywords

CMOS integrated circuits; VLSI; dielectric thin films; electron traps; integrated circuit reliability; leakage currents; vapour deposition; 1.5 nm; MOSFET performance; TiO/sub 2/-Si/sub 3/N/sub 4/; deep sub-micron CMOS technology; gate leakage current; interface quality; jet-vapor deposition; n-channel field-effect transistors; p-channel field-effect transistors; reliability; trap density; ultra-thin gate dielectric; Annealing; CMOS technology; Crystallization; Degradation; Dielectric materials; High K dielectric materials; High-K gate dielectrics; Leakage current; MOSFET circuits; Temperature;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823864

Filename

823864