A low-power static frequency divider circuit in bipolar technology

Author

Toh, K.Y. ; Tzeng, Yen C. ; Warnock, J.D. ; Petrillo, E.J. ; Chuang, Kent C T ; Sun, Jack Y C

Author_Institution

IBM, Yorktown Heights, NY, USA

fYear

1992

Firstpage

163

Lastpage

165

Abstract

A low-power silicon bipolar frequency divider circuit using AC-coupled active pull-down emitter-coupled-logic (ECL)-like circuitry is described. The divide-by-eight circuit consists of three identical divide-by-two modules in cascade. The clock is brought in through an emitter-follower, and the output of the divider is buffered through an emitter-follower output stage. The divide-by-two module consists of a pair of master-slave flip-flops. A maximum clocking frequency of 2.5 GHz at a record low power of 1.7 mW per flip-flop has been realized. The performance can be extended to 6 GHz at 5 mW per flip-flop

Keywords

bipolar integrated circuits; elemental semiconductors; emitter-coupled logic; flip-flops; frequency dividers; integrated logic circuits; silicon; 1.7 to 5 mW; 2.5 to 6 GHz; AC-coupled; active pull-down ECL; bipolar technology; clocking frequency; divide-by-eight circuit; divide-by-two module; emitter-coupled-logic; emitter-follower; low-power; master-slave flip-flops; static frequency divider circuit; Aging; Circuit simulation; Clocks; Data communication; Flip-flops; Frequency conversion; Latches; Reduced instruction set computing; Switches; Switching circuits;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0727-5

Type

conf

DOI

10.1109/BIPOL.1992.274059

Filename

274059