Title :
A low-jitter and low-power clock generator
Author :
Huang, Jiwei ; Tao, Liang ; Li, Zhengpin
Author_Institution :
Inst. of RF-&OE IC, Southeast Univ., Nanjing, China
Abstract :
This paper presents a phase-locked loop (PLL) for a clock generator in data communication system. The PLL exhibits simultaneously low jitter and low power consumption. Fully integrated loop filter simplifies the peripheral circuit. It has been fabricated using a 0.35 μm BiCMOS process, occupying 0.07 mm2 of silicon area. For a 50 MHz output frequency, the circuit features a 119 ps peak-to-peak jitter. At that frequency, the PLL consumes less than 6mW from a supply voltage of 3.3 V. The clock generator has been successfully applied in a receiver.
Keywords :
clocks; jitter; phase locked loops; BiCMOS process; data communication system; frequency 50 MHz; integrated loop filter; low power consumption; low-jitter clock generator; low-power clock generator; peak-to-peak jitter; peripheral circuit; phase locked loop; voltage 3.3 V; Clocks; Generators; Jitter; Noise; Phase frequency detector; Phase locked loops; Voltage-controlled oscillators; Clock Generator; Low jitter; Low power; Phase-Locked Loop; Ring Oscillator;
Conference_Titel :
Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on
Conference_Location :
Shanghai
Print_ISBN :
978-1-4244-5797-7
DOI :
10.1109/ICSICT.2010.5667706
