A low-jitter and low-power clock generator

This paper presents a phase-locked loop (PLL) for a clock generator in data communication system. The PLL exhibits simultaneously low jitter and low power consumption. Fully integrated loop filter simplifies the peripheral circuit. It has been fabricated using a 0.35 μm BiCMOS process, occupying 0.07 mm² of silicon area. For a 50 MHz output frequency, the circuit features a 119 ps peak-to-peak jitter. At that frequency, the PLL consumes less than 6mW from a supply voltage of 3.3 V. The clock generator has been successfully applied in a receiver.