Active clamp ESD protection in complementary BICMOS process

Author

Vashchenko, V.A. ; Hopper, P.J.

Author_Institution

Nat. Semicond. Corp., Santa Clara, CA, USA

fYear

2010

Firstpage

388

Lastpage

390

Abstract

Abstract A small footprint active clamp design with low voltage CMOS and high voltage BJT components in complementary BiCMOS process is proposed, analyzed by simulation and experimentally validated. The new clamp is composed from stacked NMOS driver to achieve appropriate voltage tolerance and power BJT. Both NPN and PNP- based versions of the clamp are compared to the stacked NMOS clamp.

Keywords

BiCMOS integrated circuits; bipolar transistors; electrostatic discharge; active clamp ESD protection; complementary BICMOS process; electrostatic discharge; high voltage BJT component; low voltage CMOS; power BJT; small footprint active clamp design; stacked NMOS clamp; stacked NMOS driver; voltage tolerance; BiCMOS integrated circuits; CMOS integrated circuits; Clamps; Driver circuits; Earth Observing System; Electrostatic discharge; MOS devices;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667707

Filename

5667707

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1638679