A 10 Gb/s receiver with equalizer and on-chip ISI monitor in 0.11 μm CMOS

Author

Tomita, Yasumoto ; Kibune, Masaya ; Ogawa, Junji ; Walker, William W. ; Tamura, Hirotaka ; Kuroda, Tadahiro

Author_Institution

Dept. of Electron. & Electr. Eng., Keio Univ., Yokohama, Japan

fYear

2004

Firstpage

202

Lastpage

205

Abstract

This paper presents a 10 Gb/s receiver that consists of an equalizer, an inter-symbol interference (ISI) monitor, and a clock and data recovery (CDR) unit. The Cherry-Hooper topology was employed to realize an adjustable high-bandwidth equalizer with reduced area and power consumption, without using on-chip inductors. The ISI monitor measures the post-cursor and pre-cursor ISI in the equalizer output. The ISI measurement is achieved using a switched-capacitor correlator. A test chip was fabricated in 0.11 μm CMOS. The areas and power consumptions are 47 μm×85 μm and 13.2 mW for the equalizer and 145 μm×80 μm and 10 mW for the ISI monitor.

Keywords

CMOS integrated circuits; equalisers; intersymbol interference; 0.11 μm CMOS; 0.11 micron; 10 Gb/s receiver; 10 Gbit/s; 10 mW; 13.2 mW; 47 micron; 85 micron; Cherry-Hooper topology; adjustable high-bandwidth equalizer; clock and data recovery unit; equalizer; inter-symbol interference monitor; on-chip ISI monitor; reduced area; reduced power consumption; Clocks; Correlators; Energy consumption; Equalizers; Inductors; Intersymbol interference; Monitoring; Semiconductor device measurement; Testing; Topology;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346559

Filename

1346559