A sub-nanosecond 9-bit accurate ECL comparator using cascaded complementary gain stages

Author

Stetzler, T.D. ; Flemming, Terry E. ; Koullias, Iconomos A.

Author_Institution

AT&T Microelectron., Reading, PA, USA

fYear

1992

Firstpage

139

Lastpage

142

Abstract

A 960-ps propagation delay, 0.5-mV-offset-voltage, emitter-coupled-logic (ECL)-compatible comparator with increased common mode range was designed and fabricated in the CBIC-V complementary bipolar process featuring 10-GHz NPN and 4.3-GHz PNP transistors. This low-offset, subnanosecond comparator was implemented in a semicustom linear array designed for high-performance circuits. Cascaded complementary gain stages using a modified emitter-coupled pair amplifier design permits operation from 3 V to 10 V supplies with less than 100-ps dispersion. A summary of the comparator experimental results is given

Keywords

bipolar integrated circuits; comparators (circuits); emitter-coupled logic; integrated logic circuits; 10 GHz; 3 to 10 V; 4.3 GHz; 960 ps; CBIC-V; ECL comparator; cascaded complementary gain stages; complementary bipolar process; emitter-coupled pair amplifier design; emitter-coupled-logic; propagation delay; semicustom linear array; subnanosecond delay; Circuits; Design optimization; Photonic band gap; Power supplies; Propagation delay; Rails; Signal resolution; Signal sampling; Temperature; Voltage;

fLanguage

English

Publisher

ieee

Conference_Titel

Bipolar/BiCMOS Circuits and Technology Meeting, 1992., Proceedings of the 1992

Conference_Location

Minneapolis, MN

Print_ISBN

0-7803-0727-5

Type

conf

DOI

10.1109/BIPOL.1992.274065

Filename

274065