Towards evolving industry-feasible intrinsic variability tolerant CMOS designs

As the size of CMOS devices is approaching the atomic level, the increasing intrinsic device variability is leading to higher failure rates in conventional CMOS designs. This paper introduces a design tool capable of evolving CMOS topologies using a modified form of Cartesian genetic programming and a multi-objective strategy. The effect of intrinsic variability within the design is then analysed using statistically enhanced SPICE models based on 3D-atomistic simulations. The goal is to produce industry-feasible topology designs which are more tolerant to the random fluctuations that will be prevalent in future technology nodes. The results show evolved XOR and XNOR CMOS topologies and compare the impact of threshold voltage variation on the evolved designs with those from a standard cell library.