DocumentCode :
1638848
Title :
An investigation on parasitic couplings and feedback loops in the CMOS circuits
Author :
Deng, A.C. ; Tuan, J.F. ; Ong, L.W.
Author_Institution :
Dept. of Electr. Eng., Texas A&M Univ., Austin, TX, USA
fYear :
1989
Firstpage :
864
Abstract :
Two major problems in network partitioning are investigated: the parasitic coupling capacitances between the partitioned subcircuits, and the feedback loops. The coupling capacitance effect is shown to be negligible if state transitions in the neighboring subcircuits do not occur simultaneously. A decoupling criterion is developed to decide whether the coupling between the subcircuits is negligible. A loop-merging algorithm is developed to handle feedback in loops such a manner that the network topology is described by a unidirectional signal path graph, which makes it possible for a single-sweep Gauss-Seidel relaxation. Moreover, an event-driven algorithm is proposed to take advantage of the hierarchical loop structure resulting from the merge algorithm
Keywords :
CMOS integrated circuits; capacitance; feedback; flip-flops; integrated logic circuits; network topology; CMOS circuits; JK flip-flop circuit; decoupling criterion; event-driven algorithm; feedback loops; hierarchical loop structure; loop-merging algorithm; neighboring subcircuits; network partitioning problems; network topology; parasitic coupling capacitances; partitioned subcircuits; single-sweep Gauss-Seidel relaxation; state transitions; subcircuit coupling; unidirectional signal path graph; Circuit simulation; Coupling circuits; Feedback circuits; Feedback loop; Intelligent networks; MOSFET circuits; Network topology; Parasitic capacitance; Partitioning algorithms; Switches;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
Type :
conf
DOI :
10.1109/ISCAS.1989.100488
Filename :
100488
Link To Document :
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