Gate-level optimization of polymorphic circuits using Cartesian Genetic Programming

Polymorphic digital circuits contain ordinary and polymorphic gates. In the past, Cartesian genetic programming (CGP) has been applied to synthesize polymorphic circuits at the gate level. However, this approach is not scalable. Experimental results presented in this paper indicate that larger and more efficient polymorphic circuits can be designed by a combination of conventional design methods (such as BDD, Espresso or ABC system) and evolutionary optimization (conducted by CGP). Proposed methods are evaluated on two benchmark circuits - multiplier/sorter and parity/majority circuits of variable input size.