Title :
A simulation-based fast algorithm for CMOS circuit speed optimization
Author :
Yuan, Jiren ; Svensson, Christer
Author_Institution :
LSI Design Center, IFM, Linkoping Univ., Sweden
Abstract :
A new algorithm used in a CMOS circuit speed optimization tool, SLOP version 2, is presented. In this algorithm, no user direction is involved except the circuit description. Macromodeling and verification techniques are used to improve the speed and the completeness. The delay calculation is improved by considering the node coupling effect. In most cases, the delay errors are less than ±15% compared with SPICE simulation. The CPU time is substantially reduced, especially for pipelined circuits
Keywords :
CMOS integrated circuits; circuit CAD; delays; integrated logic circuits; logic CAD; CMOS circuit speed optimization tool; CPU time; SLOP version 2; SPICE simulation; circuit description; completeness improvement; delay calculation; delay errors; macromodelling techniques; node coupling effect; pipelined circuits; speed improvement; verification techniques; Central Processing Unit; Circuit simulation; Clocks; Coupling circuits; Delay effects; Design optimization; Iterative algorithms; Latches; Semiconductor device modeling; Switches;
Conference_Titel :
Circuits and Systems, 1989., IEEE International Symposium on
Conference_Location :
Portland, OR
DOI :
10.1109/ISCAS.1989.100489
