A Spice-compatible flash EEPROM model feasible for transient and program/erase cycling endurance simulation

Author

Chung, S.S. ; Yih, C.-M. ; Wu, S.S. ; Chen, H.H. ; Gary Hong

Author_Institution

Dept. of Electron. Eng., Nat. Chiao Tung Univ., Hsinchu, Taiwan

fYear

1999

Firstpage

179

Lastpage

182

Abstract

A complete Spice-compatible model for stacked-gate flash EEPROM cells has been successfully developed. It includes an accurate DC I-V model, a gate current model for Channel Hot Electron (CHE) programming; and a channel Fowler-Nordheim (FN) current model for erase. Program and erase induced oxide damage are also included in the model. For the first time, it allows the simulation of the programming/erase transient and the P/E cycling endurance characteristics using the present analytical approach. It provides an easy way for applications to cell design optimization and reliability evaluation for device and circuit designers.

Keywords

PLD programming; SPICE; flash memories; hot carriers; integrated circuit modelling; integrated circuit reliability; integrated memory circuits; transient analysis; tunnelling; CHE programming; DC I-V model; FN current model; MOSFET; Spice-compatible model; cell design optimization; channel Fowler-Nordheim current model; channel hot electron programming; erase induced oxide damage; flash EEPROM model; gate current model; program induced oxide damage; program/erase cycling endurance simulation; programming/erase transient; reliability evaluation; stacked-gate flash EEPROM cells; transient simulation; Analytical models; CMOS technology; Channel hot electron injection; Circuit simulation; Design optimization; EPROM; Flash memory; Flash memory cells; Nonvolatile memory; Transient analysis;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823874

Filename

823874