A low-power switched-current CDMA matched filter with on-chip V-I and I-V converters

Author

Yamasaki, T. ; Nakayama, Taiki ; Shibata, Tadashi

Author_Institution

Dept. of Electron. Eng., Univ. of Tokyo, Japan

fYear

2004

Firstpage

214

Lastpage

217

Abstract

A low-power and compact CDMA matched filter has been developed using the switched-current technology. On-chip V-I and I-V converters featuring moderate linear characteristics have been developed for the chip. The low-power operation has been achieved by the sub-block architecture and the reduced current flowing in current-memory cells. A low-power clock-on-demand shift-register has also been developed. The 256-chip matched filter fabricated in a 0.35-μm technology demonstrated 1.95 mW operation at 8Mchip/s with 2 V power supply, occupying 0.54 mm².

Keywords

CMOS integrated circuits; code convertors; code division multiple access; 0.35 micron; 1.95 mW; 2 V; clock-on-demand shift-register; current-memory cells; low-power operation; low-power switched-current CDMA matched filter; matched filter; moderate linear characteristics; on-chip converters; reduced current; sub-block architecture; CMOS technology; Clocks; Dynamic voltage scaling; Matched filters; Multiaccess communication; Parasitic capacitance; Power supplies; Surface acoustic waves; Switches; Switching converters;

fLanguage

English

Publisher

ieee

Conference_Titel

VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on

Print_ISBN

0-7803-8287-0

Type

conf

DOI

10.1109/VLSIC.2004.1346564

Filename

1346564