A novel and simple 0.18µm CMOS sub-1V low-dropout regulator

Author

Wu, Zhi-Meng ; Feng, Quan-Yuan ; Xiang, Qian-Yin

Author_Institution

Inst. of Microelectron., Southwest Jiaotong Univ., Chengdu, China

fYear

2010

Firstpage

357

Lastpage

359

Abstract

A CMOS capacitor-free low-dropout (LDO) voltage regulator with 0.65-1.8 V power supply is presented. Positive feedback is used to build the differential computation of the error amplifier and the positive feedback gain is less than unity to ensure the stability. The LDO is designed in TSMC 0.18 μm CMOS processes. The maximum output current of the LDO is 50 mA at an output of 0.5 V. The simulation results show the average settling time of 9.9 μs can be achieved with 0.5% error for load current change between 5 mA and 50 mA, and the line and load regulations are 0.847%/V and 22.8 ppm/mA, respectively.

Keywords

CMOS integrated circuits; amplifiers; voltage regulators; CMOS capacitor-free low-dropout voltage regulator; CMOS process; current 50 mA; error amplifier; positive feedback gain; power supply; size 0.18 mum; voltage 0.5 V; voltage 0.65 V to 1.8 V; CMOS integrated circuits; Capacitors; Differential amplifiers; Load modeling; Regulators; Simulation; Voltage control; Low dropout voltage regulator; capacitor free; positive feedback;

fLanguage

English

Publisher

ieee

Conference_Titel

Solid-State and Integrated Circuit Technology (ICSICT), 2010 10th IEEE International Conference on

Conference_Location

Shanghai

Print_ISBN

978-1-4244-5797-7

Type

conf

DOI

10.1109/ICSICT.2010.5667718

Filename

5667718