DocumentCode
1639022
Title
A 0.6-4.2V low-power configurable PLL architecture for 6 GHz-300 MHz applications in a 90 nm CMOS process
Author
Raha, Prasun
Author_Institution
Texas Instrum. Inc., Dallas, TX, USA
fYear
2004
Firstpage
232
Lastpage
235
Abstract
This paper presents a configurable feed-forward PLL architecture with supply-independent loop dynamics for low power, multiphase clock-generation in power-sensitive DSP cores using dynamic voltage scaling techniques in a 90 nm CMOS process. A four-stage, current-controlled ring-oscillator based PLL is shown to be able to generate 6 GHz-300 MHz frequencies in a 90 nm CMOS process with a power supply range of 1.2-0.6 V. PLL power consumption is 10 mW@5 GHz and 300 uW@500 MHz. The PLL die area is 0.10 mm2.
Keywords
CMOS integrated circuits; feedforward; phase locked loops; power consumption; 0.6 to 4.2 V; 0.6-4.2V low-power configurable PLL architecture; 6 GHz to 300 MHz; 90 nm; 90 nm CMOS process; configurable feed-forward PLL architecture; current-controlled ring-oscillator; dynamic voltage scaling techniques; multiphase clock-generation; supply-independent loop dynamics; CMOS process; Clocks; Digital signal processing; Dynamic voltage scaling; Energy consumption; Feedforward systems; Frequency; Phase locked loops; Power generation; Power supplies;
fLanguage
English
Publisher
ieee
Conference_Titel
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN
0-7803-8287-0
Type
conf
DOI
10.1109/VLSIC.2004.1346570
Filename
1346570
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