DocumentCode :
1639027
Title :
A background optimization method for PLL by measuring phase jitter performance
Author :
Dosho, Shiro ; Yanagisawa, Naoshi
Author_Institution :
Matsushita Electr. Ind. Co. Ltd., Osaka, Japan
fYear :
2004
Firstpage :
236
Lastpage :
239
Abstract :
This paper describes a background (BG) optimization method for Phase-Locked-Loop(PLL). Measuring the phase shift of the voltage controlled oscillator(VCO) at each input reference clock, we can determine the phase jitter performance exactly. Using the combination of the global optimization method at initial phase and the local optimization method for background calibration always gives the PLL the smallest jitter performance under any conditions.
Keywords :
CMOS integrated circuits; integrated circuit measurement; jitter; phase locked loops; voltage-controlled oscillators; PLL; background optimization method; global optimization method; measuring phase jitter performance; phase jitter performance; phase shift; voltage controlled oscillator; Calibration; Charge pumps; Circuits; Clocks; Jitter; Optimization methods; Phase detection; Phase locked loops; Phase measurement; Voltage-controlled oscillators;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
Print_ISBN :
0-7803-8287-0
Type :
conf
DOI :
10.1109/VLSIC.2004.1346571
Filename :
1346571
Link To Document :
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