A parallel implementation of nonlinear steady state analysis based on time-domain Newton-Raphson algorithm

Author

Adachi, Takehiko ; Kai, Satoshi ; Iriyama, Toshihisa

Author_Institution

Div. of Electr. & Comput. Eng., Yokohama Nat. Univ., Japan

fYear

1989

Firstpage

889

Abstract

A parallel implementation of the time-domain Newton-Raphson algorithm is presented. A theoretical expression for speedup was obtained, and simulations were made of several sample circuits. There is a fairly good agreement between the theoretically expected and simulated speedups. It has been shown that a speedup of up to (M-1) can be attained on M processors. Average processor utilization is introduced to analyze the processor load imbalance, and the improvement attained by the proposed method is analyzed in terms of processor utilization

Keywords

bipolar transistor circuits; circuit analysis computing; linear integrated circuits; nonlinear network analysis; sensitivity analysis; time-domain analysis; M processors; analogue IC; average processor utilization; bipolar transistor circuits; nonlinear steady state analysis; parallel implementation; processor load imbalance; sensitivity analysis; simulated speedup; theoretical speedup expression; time-domain Newton-Raphson algorithm; Algorithm design and analysis; Analog integrated circuits; Analytical models; Circuit simulation; Computational modeling; Computer aided analysis; Steady-state; Time domain analysis; Voltage; Workstations;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100494

Filename

100494