Low delay-high compact FIR filter using reduced wallace multiplier

There are different entities that one would like to optimize when designing a VLSI circuit. The design of an efficient integrated circuit in terms of power, area, and speed simultaneously, has become a very challenging problem. Finite Impulse Response filters are the lead for DSP applications and communication. FIR filters has the multipliers of its heart of the system. So the improvement in the multiplier design will make the change in the FIR filter. In depth for multipliers adder is the main system. By reducing the parameters of both adder and multiplier will get a better result in computing the filtering operations. In this paper the adder has a modification by the reduced carry save adder. By changing this propagation of carry. The proposed design is simulated in ModelSim 6.3c and synthesis is done in Xilinx ISE 10.1. Finally the design is implemented in Spartan-3 FPGA.