RF Hardware Modeling of a Direct Conversion Receiver Using SDMA

A study of the effects of front-end impairments on the overall performance of a direct conversion wireless receiver using SDMA is presented. A system-level model, simulated with Verilog-AMS and using Verilog behavioral blocks, is used to evaluate the performance of the receiver under non-ideal RF circuit conditions. Design issues inherent to direct conversion receivers, including IIP2, quadrature mismatches, LO self-mixing and 1/f noise are included in the RF models. In addition, noise figure, IIP3 and LO phase noise are modeled. Simulation results show that the use of SDMA is able to significantly boost system performance and compensate for much of the RF impairments. For example, it is seen that I/Q amplitude and phase mismatches of 5 dB and 32deg respectively, can be tolerated while still providing acceptable bit error rate.