Title :
Integration of ultrathin (1.6/spl sim/2.0 nm) RPECVD oxynitride gate dielectrics into dual poly-Si gate submicron CMOSFETs
Author :
Yang, H. ; Lucovsky, G.
Author_Institution :
Dept. of Electr. & Comput. Eng., North Carolina State Univ., Raleigh, NC, USA
Abstract :
Detailed comparisons indicates superior performance and reliability in dual poly-Si gate CMOSFETs in which oxynitride alloys have been substituted for nitrides of stacked oxide/nitride dielectrics with Tox-eq /spl sim/2 nm. Similar comparisons using CMOSFETs with optimized oxide/oxynitride stacked dielectrics (Tox-eq /spl sim/1.67 nm) which also include interface plasma-nitridation at the one monolayer level are reported. These also indicate superior performance and reliability with respect to CMOSFET devices with stacked oxide/nitride dielectrics, including an additional /spl sim/10/spl times/ decrease in direct tunneling due to the interface nitridation.
Keywords :
CMOS integrated circuits; MOSFET; dielectric thin films; integrated circuit reliability; integrated circuit technology; nitridation; plasma CVD coatings; silicon; tunnelling; 1.6 to 2 nm; SiNO; direct tunneling reduction; dual poly-Si gate MOSFETs; dual polysilicon gate; interface plasma-nitridation; oxynitride gate dielectrics; reliability; remote plasma-assisted CVD; stacked oxide/nitride dielectrics; submicron CMOSFETs; ultrathin RPECVD gate dielectrics; Annealing; CMOSFETs; Dielectric devices; Dielectric substrates; Dielectric thin films; MOSFET circuits; Oxidation; Plasma devices; Plasma materials processing; Tunneling;
Conference_Titel :
Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International
Conference_Location :
Washington, DC, USA
Print_ISBN :
0-7803-5410-9
DOI :
10.1109/IEDM.1999.823889
