Title :
Optimization of Moore FSM on system-on-chip using PAL technology
Author :
Barkalov, Alexander ; Titarenko, Larysa ; Chmielewski, Slawomir
Author_Institution :
Inst. of Comput. Eng. & Electron., Univ. of Zielona Gora, Zielona Gora, Poland
Abstract :
Method of decrease of number of PAL macrocells in circuit of Moore FSM is proposed. Method is based on use of free outputs of embedded memory blocks to represent a code of a class of the pseudoequivalent states. Proposed approach permits to decrease the hardware amount without decrease of a digital system performance. An example of application of proposed method is given.
Keywords :
digital systems; embedded systems; finite state machines; optimisation; programmable logic arrays; system-on-chip; Moore FSM optimization; PAL macrocells; PAL technology; digital system performance; embedded memory blocks; finite state machines; programmable logic arrays; pseudoequivalent states; system-on-chip; CPLD; Moore FSM; PAL; SoC; design;
Conference_Titel :
Modern Problems of Radio Engineering, Telecommunications and Computer Science, 2008 Proceedings of International Conference on
Conference_Location :
Lviv-Slavsko
Print_ISBN :
978-966-553-678-9
