Low area and high speed confined multiplier using multiplexer based full adder

This paper presents a comparative study of Field Programmable Gate Array (FPGA) implementation of standard multipliers using RTL simulation. Multiplier plays a vital role in digital signal processing (DSP) applications such as finite impulse response (FIR) and discrete cosine transforms (DCT) etc. So by changing the multiplier efficiency the above applications will achieve a higher efficiency. In this the numbers of single bit adders are reduced and also it will be replaced by multiplexers. So that the LUT´s FPGA has utilized fully by occupying in the lower number of slices. Significant reduction in FPGA resources, delay, and power can be achieved using confined Wallace multiplier design. These multiplication techniques are designed by using RTL simulation and it is simulated in ModelSim 6.3c and synthesis is done in Xilinx ISE 10.1. Finally the design is implemented in Spartan-3 FPGA.