Partition based heuristics for gate matrix layout

Author

Lakhani, G. ; Rathinaswami, S.

Author_Institution

Texas Tech. Univ., Lubbock, TX, USA

fYear

1989

Firstpage

897

Abstract

An extension is presented of a concept called dynamic-net-list representation for CMOS circuit layout in the gate-matrix style. With this extension, delayed bindings for nets representing complex connections, such as serial-parallel or parallel-serial connected transistors, can be handled. The authors also develop a heuristic for obtaining a fast feasible net realization. Experimental results that show improvement over previously published results are presented

Keywords

CMOS integrated circuits; circuit layout CAD; heuristic programming; CMOS circuit layout; complex connection representing nets; delayed bindings; dynamic-net-list representation; fast feasible net realization; gate matrix layout; parallel-serial connected transistors; partition based heuristics; result improvement; serial-parallel connected transistors; CMOS logic circuits; Concurrent computing; Network address translation;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 1989., IEEE International Symposium on

Conference_Location

Portland, OR

Type

conf

DOI

10.1109/ISCAS.1989.100496

Filename

100496

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1639384