Cu/poly-Si damascene gate structured MOSFET with Ta and TaN stacked barrier

Author

Matsuki, T. ; Kishimoto, K. ; Fujii, K. ; Itoh, N. ; Yoshida, K. ; Ohto, K. ; Yamasaki, S. ; Shinmura, T. ; Kasai, N.

Author_Institution

ULSI Device Dev. Lab., NEC Corp., Sagamihara, Japan

fYear

1999

Firstpage

261

Lastpage

264

Abstract

A Cu/Si layered-gate-structured MOSFET with Ta and TaN stacked barrier layers fabricated using a Cu damascene process has been developed for high-performance and reliable Si ULSI devices. A sheet resistance of 0.5 ohm/sq. was achieved with a 0.25 /spl mu/m gate length. The Ta and TaN layers guarantee reliable gate oxide (7.5 nm) after 500/spl deg/C thermal processing in nitrogen with forming gas annealing.

Keywords

CMOS integrated circuits; MOSFET; ULSI; annealing; copper; integrated circuit metallisation; integrated circuit reliability; silicon; tantalum; tantalum compounds; 0.25 micron; 500 C; 7.5 nm; Cu damascene process; Cu-Si; Cu/Si layered-gate-structured MOSFET; Cu/poly-Si damascene gate MOSFET; Ta-TaN; Ta/TaN stacked barrier; forming gas annealing; polysilicon; reliable Si ULSI devices; reliable gate oxide; sheet resistance; thermal processing; Artificial intelligence; Copper; Electrodes; Etching; Insulation; MOSFET circuits; Sheet materials; Thermal degradation; Ultra large scale integration; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823893

Filename

823893