A high density high performance 180 nm generation Etox/sup TM/ flash memory technology

Author

Fazio, A.

Author_Institution

Intel Corp., Santa Clara, CA, USA

fYear

1999

Firstpage

267

Lastpage

270

Abstract

A 180 nm-generation flash memory technology has been developed, optimized for small cell size, high performance low voltage operation and multi-level-cell and embedded logic capability. Memory cell scaling utilizes scaled trench isolation, self-aligned floating gates, cobalt salicided complementary poly gates, unlanded contacts and traditional dielectric and junction scaling. Low voltage performance is achieved with the inclusion of logic compatible NMOS and PMOS transistors, a triple well and 3 layers of metal interconnect. 16 Mbit flash memories with 0.38 /spl mu/m/sup 2/ cell size have been built on this technology as a yield and reliability test vehicle.

Keywords

CMOS memory circuits; flash memories; integrated circuit technology; low-power electronics; 16 Mbit; 180 nm; 180 nm generation memory technology; Co salicided complementary poly gates; CoSi/sub 2/; LV operation; dielectric scaling; embedded logic capability; high density Etox flash memory technology; junction scaling; low voltage operation; memory cell scaling; multi-level-cell capability; scaled trench isolation; self-aligned floating gates; three-layer metal interconnect; triple well; unlanded contacts; Cobalt; Dielectrics; Flash memory; Isolation technology; Logic testing; Low voltage; MOS devices; MOSFETs; Nonvolatile memory; Vehicles;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823894

Filename

823894