A novel gate-offset NAND cell (GOC-NAND) technology suitable for high-density and low-voltage-operation flash memories

Author

Satoh, S. ; Nakamura, T. ; Shimizu, Kazuo ; Takeuchi, K. ; Iizuka, H. ; Aritome, Seiichi ; Shirota, R.

Author_Institution

Microelectron. Eng. Lab., Toshiba Corp., Yokohama, Japan

fYear

1999

Firstpage

271

Lastpage

274

Abstract

This paper describes a novel scaled and low-voltage-operation NAND EEPROM technology with a G_ate-O_ffset NAND C_ell (GOC-NAND), which is free from program disturbance in a self-boosted program. In GOC-NAND, novel source/drain engineering is introduced for the first time. The program disturbance is decreased by two decades of magnitude in 0.1 /spl mu/m generation, without area penalty and additional process steps. Furthermore, the program disturbance is not increased by scaling and low voltage operation. Therefore, GOC-NAND is indispensable technology for gigabit-scaled NAND EEPROMs.

Keywords

CMOS memory circuits; NAND circuits; flash memories; integrated circuit technology; low-power electronics; 0.1 micron; LV flash memories; NAND EEPROM technology; gate-offset NAND cell technology; gigabit-scaled NAND EEPROMs; high-density flash memories; low-voltage-operation; program disturbance reduction; source/drain engineering; Boosting; Capacitance; Chromium; EPROM; Electronic mail; Flash memory; Impurities; Laboratories; Threshold voltage; Voltage control;

fLanguage

English

Publisher

ieee

Conference_Titel

Electron Devices Meeting, 1999. IEDM '99. Technical Digest. International

Conference_Location

Washington, DC, USA

Print_ISBN

0-7803-5410-9

Type

conf

DOI

10.1109/IEDM.1999.823895

Filename

823895