• DocumentCode
    1639667
  • Title

    SRAM design on 65nm CMOS technology with integrated leakage reduction scheme

  • Author

    Zhang, K. ; Bhattacharya, Ujjwal ; Chen, Z. ; Hamzaoglu, F. ; Murray, D. ; Vallepalli, N. ; Wang, Y. ; Zheng, B. ; Bohr, M.

  • Author_Institution
    Portland Technol. Dev., Intel Corp., Hillsboro, OR, USA
  • fYear
    2004
  • Firstpage
    294
  • Lastpage
    295
  • Abstract
    A 4Mb SRAM is designed and fabricated on a 65nm CMOS technology. It features a 0.57 μm2 6T cell with large noise margin down to 0.7V for low-voltage operation. The fully synchronized subarray contains an integrated leakage reduction scheme with sleep transistor. It also has a built-in programmable defect "screen" circuit for high volume manufacturing.
  • Keywords
    CMOS memory circuits; SRAM chips; integrated circuit noise; leakage currents; 0.7 V; 4 Mbit; 65 nm; 65nm CMOS technology; SRAM design; fully synchronized subarray; integrated leakage reduction scheme; large noise margin; low-voltage operation; sleep transistor; CMOS technology; Circuit topology; Decoding; Frequency synchronization; Integrated circuit technology; Latches; Manufacturing; Random access memory; Sleep; Timing;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    VLSI Circuits, 2004. Digest of Technical Papers. 2004 Symposium on
  • Print_ISBN
    0-7803-8287-0
  • Type

    conf

  • DOI
    10.1109/VLSIC.2004.1346592
  • Filename
    1346592
    • Link To Document
    https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1639667