Parallel automated test pattern generation on the Connection Machine

Author

Mayor, Pankaj ; Pitchumani, Vijay ; Narayanan, Vinod

Author_Institution

Dept. of Electr. & Comput. Eng., Syracuse Univ., NY, USA

fYear

1989

Firstpage

942

Abstract

The authors present an SIMD (single-instruction multiple-data) algorithm for automated test pattern generation. An effort was made to parallelize the individual steps of FAN by employing the massive parallelism of the Connection Machine. The algorithm considers one fault at a time and generates a test for it. Fine-grain parallelism is achieved by several gates within a level simultaneously doing multiple backtrace or forward simulation

Keywords

automatic test equipment; automatic testing; electronic engineering computing; fault location; logic testing; parallel algorithms; Connection Machine; SIMD; automated test pattern generation; fine grain parallelism; forward simulation; massive parallelism; multiple backtrace; single-instruction multiple-data; Algorithm design and analysis; Automatic test pattern generation; Circuit faults; Circuit testing; Computer architecture; Concurrent computing; Logic; Metalworking machines; Parallel processing; Test pattern generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Test Conference, 1989. Proceedings. Meeting the Tests of Time., International

Conference_Location

Washington, DC

Type

conf

DOI

10.1109/TEST.1989.82394

Filename

82394

Link To Document

https://search.isc.ac/dl/search/defaultta.aspx?DTC=49&DC=1639684